View DS89C420-QNG_1905439.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 of 47 rev: 081805 note: some revisions of this device may incorporate deviations from published specifications known as errata. multiple revisions of any device may be simultaneously available through various sales channels. for information about device errata, click here: www.maxim-ic.com/errata . - general description the ds89c420 offers the highest performance available in 8051-compatible microcontrollers. it features a redesigned processor core that executes every 8051 instruction (depending on the instruction type) up to 12 times faster than the original for the same crystal speed. typical applications see a speed improvement of 10 times using the same code and crystal. the ds89c420 offers a maximum crystal speed of 33mhz, achieving execution rates up to 33 million instructions per second (mips). the ds89c430 ultra-high-speed flash microcontroller is an improved version of the ds89c420. the device offers more features, such as in-application programming, for approximately the same price. engineers interested in the ds89c420 are encouraged to compare both devices when selecting an ultra-high-speed flash microcontroller. applications ordering information part temp range max clock speed (mhz) pin- package ds89c420-mng -40c to +85c 25 40 pdip DS89C420-QNG -40c to +85c 25 44 plcc ds89c420-eng -40c to +85c 25 44 tqfp ds89c420-mcl 0c to +70c 33 40 pdip ds89c420-qcl 0c to +70c 33 44 plcc ds89c420-ecl 0c to +70c 33 44 tqfp ds89c420-mnl -40c to +85c 33 40 pdip ds89c420-qnl -40c to +85c 33 44 plcc ds89c420-enl -40c to +85c 33 44 tqfp features 80c52 compatible 8051 pin- and instruction-set compatible four bidirectional i/o ports three 16-bit timer counters 256 bytes scratchpad ram on-chip memory 16kb flash memory in-system programmable through serial port 1kb sram for movx romsize feature selects internal program memory size from 0 to 16k allows access to entire external memory map dynamically adjustable by software high-speed architecture 1 clock-per-machine cycle dc to 33mhz operation single-cycle instruction in 30ns optional variable length movx to access fast/slow peripherals dual data pointers with auto increment/decrement and toggle select supports four paged modes power management mode programmable clock divider automatic hardware and software exit two full-duplex serial ports programmable watchdog timer 13 interrupt sources (six external) five levels of interrupt priority power-fail reset early warning power-fail interrupt the ultra-high-speed flash microcontroller user?s guide should be used in conjunction with this data sheet. download it at www.maxim-ic.com/microcontrollers . pin configurations appear at end of data sheet. data logging vending security and door access control automotive test equipment building energy control and management motor control gaming equipment uninterruptible power supplies magstripe reader/scanner programmable logic controllers consumer electronics telephones industrial control and automation appliances (washers, microwaves, etc.) www.maxim-ic.com ds89c420 ultra-high-speed microcontrolle r
ds89c420 ultra-high-speed microcontroller 2 of 47 absolute maximum ratings voltage range on any pin relative to ground -0.3v to (v cc + 0.5v) voltage range on v cc relative to ground -0.3v to +6.0v operating temperature range -40c to +85c storage temperature range -55c to +125c soldering temperature see ipc/ jedec j-std-020 specification stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of t he specifications is not implied. exposure to absolute maximum rating conditions for extended periods can affect device reliability. dc electrical characteristics (v cc = 4.5v to 5.5v; t a = -40c to +85c.) (note 1) parameter symbol conditions min typ max units supply voltage v cc (notes 2, 13) 4.5 5.0 5.5 v power-fail warning v pfw (notes 2, 12) 4.2 4.375 4.6 v reset trip point v rst (notes 2, 12, 13) 3.95 4.125 4.35 v 33mhz 100 150 supply current active mode (note 3) i cc 25mhz 75 125 ma 33mhz 40 50 supply current idle mode (note 4) i idle 25mhz 40 50 ma supply current stop mode, bandgap disabled i stop (note 5) 40 ma supply current stop mode, bandgap enabled i spbg (note 5) 40 ma input low level v il (note 2) -0.3 +0.8 v input high level v ih (note 2) 2.0 v cc + 0.3 v input high level xtal and rst v ih2 (note 2) 3.5 v cc + 0.3 v output low voltage; port 1 and 3 at i ol = 1.6ma v ol1 (note 2) 0.15 0.45 v output low voltage; port 0 and 2, ale, psen at i ol = 3.2ma v ol2 (note 2) 0.15 0.45 v output high voltage; port 1, 2, and 3, ale, psen at i oh = -50 a v oh1 (notes 2, 7) 2.4 v output high voltage; port 1, 2, and 3 at i oh = -1.5ma v oh2 (notes 2, 8) 2.4 v output high voltage; port 0 and 2 in bus mode at i oh = -8ma v oh3 (notes 2, 6) 2.4 v output high voltage, rst at i ol = - 0.4ma v oh4 (notes 2, 14) 2.4 v input low current; port 1, 2, and 3 at 0.4v i il -55 a transition current from 1 to 0; port 1, 2, and 3 at 2v i tl (note 9) -650 a input leakage current, port 0 in i/o mode and ea i l (note 11) -10 +10 a input leakage current, port 0 in bus mode i l (note 10) -300 +300 a rst pulldown resistance r rst (note 11) 50 170 k
ds89c420 ultra-high-speed microcontroller 3 of 47 note 1: specifications to -40c are guaranteed by design and not production tested. note 2: all voltages are referenced to ground. note 3: active current is measured with a 25mhz/33mhz clock source driving xtal1, v cc = rst = 5.5v. all other pins disconnected. note 4: idle mode current measured with a 25mhz/33mhz clock source driving xtal1, v cc = 5.5v, rst at ground. all other pins disconnected. note 5: stop mode measured with xtal and rst grounded, v cc = 5.5v. all other pins disconnected. note 6: when addressing external memory. note 7: rst = 5.5v. this condition mimics the operation of pins in i/o mode. note 8: during a 0-to-1 transition, a one-shot drives the ports hard for two clock cycles. this measurement reflects a port pin in tra nsition mode. note 9: ports 1, 2, and 3 source transition current when being pulled down externally. the current reaches its maximum at approximatel y 2v. note 10: this port is a weak address holding latch in bus mode. peak current occurs near the input transition point of the holding latc h at approximately 2v. note 11: rst = 5.5v. port 0 floating during reset and when in the logic-high state during i/o mode. note 12: while the specifications for v pfw and v rst overlap, the design of the hardware makes it such that this is not possible. within the ranges given, there is a guaranteed separation between these two voltages. note 13: the user should note that this part is tested and guaranteed to operate down to 4.5v (10%) and that v rst (min) is specified below that point. this indicates that there is a range of voltages [v min to v rst (min)] where the processor?s operation is not guaranteed, but the reset trip point has not been reached. this should not be an issue in most applications, but should be considered when proper operation must be maintained at all times. for these applications, it may be desirable to use a more accurate external reset. note 14: guaranteed by design.
ds89c420 ultra-high-speed microcontroller 4 of 47 ac characteristics (v cc = 4.5v to 5.5v; t a = -40c to +85c)* ( figure 1 , figure 2 , and figure 3 ) 1 cycle page mode 1 2 cycle page mode 1 4 cycle page mode 1 page mode 2 non-page mode parameter symbol min max min max min max min max min max units 0 25 0 25 0 25 0 25 0 25 external oscillator (25mhz, 33mhz) 0 33 0 33 0 33 0 33 0 33 1 25 1 25 1 25 1 25 1 25 system clock (note 1) external crystal (25mhz, 33mhz) 1 / t clcl 1 33 1 33 1 33 1 33 1 33 mhz ale pulse width (note 2) t lhll 0.5t clcl - 2 + t stc3 t clcl - 2 + t stc3 2t clcl - 4 + t stc3 1.5t clcl - 5 + t stc3 1.5t clcl - 5 + t stc3 ns port 0 instruction address valid to ale low t avll t clcl - 2 0.5t clcl - 2 ns port 2 instruction address valid to ale low t avll2 0.5t clcl - 4 0.5t clcl - 4 1.5t clcl - 5 0.5t clcl - 2 t clcl - 2 ns port 0 data addressvalid to ale low t avll3 t clcl - 2 + t stc3 0.5t clcl - 2 + t stc3 ns program address hold after ale low t llax 0.5t clcl - 8 1.5t clcl - 8 2.5t clcl - 8 0.5t clcl - 8 0.5t clcl - 8 ns address hold after ale low movx write t llax2 0.5t clcl - 8 + t stc4 1.5t clcl - 8 + t stc4 2.5t clcl - 8 + t stc4 0.5t clcl - 8 + t stc4 0.5t clcl - 8 + t stc4 ns address hold after ale low movx read t llax3 0.5t clcl - 8 + t stc4 1.5t clcl - 8 + t stc4 2.5t clcl - 8 + t stc4 0.5t clcl - 8 + t stc4 0.5t clcl - 8 + t stc4 ns ale low to valid instruction in t lliv 2.5t clcl - 20 2.5t clcl - 20 ns ale low to psen low t llpl 1.5t clcl - 6 0.5t clcl - 6 ns psen pulse width for program fetch t plph t clcl - 5 t clcl - 5 2t clcl - 5 t clcl - 5 2t clcl - 5 ns
ds89c420 ultra-high-speed microcontroller 5 of 47 1 cycle page mode 1 2 cycle page mode 1 4 cycle page mode 1 page mode 2 non-page mode parameter symbol min max min max min max min max min max units psen low to valid instruction in t pliv t clcl - 18 t clcl - 18 2t clcl - 18 t clcl - 18 2t clcl - 18 ns input instruction hold after psen t pxix 0 0 0 0 0 ns input instruction float after psen t pxiz t clcl - 5 t clcl - 5 ns port 0 address to valid instruction in t aviv0 1.5t clcl - 20 3t clcl - 20 ns port 2 address to valid instruction in t aviv2 t clcl - 18 1.5t clcl - 18 2.5t clcl - 18 3t clcl - 20 3.5t clcl - 20 ns psen low to port 0 address float t plaz 0 0 ns rd pulse width (p3.7) (note 2) t rlrh t clcl - 5 + t stc1 t clcl - 5 + t stc1 2t clcl - 5 + t stc1 2t clcl - 5 + t stc1 2t clcl - 5 + t stc1 ns wr pulse width (p3.6) (note 2) t wlwh t clcl - 5 + t stc1 t clcl - 5 + t stc1 2t clcl - 5 + t stc1 2t clcl - 5 + t stc1 2t clcl - 5 + t stc1 ns rd (p3.7) low to valid data in (note 2) t rldv t clcl - 15 + t stc1 t clcl - 15 + t stc1 2t clcl - 15 + t stc1 2t clcl - 15 + t stc1 2t clcl - 15 + t stc1 ns data hold after rd (p3.7) t rhdx 0 0 0 0 0 ns data float after rd (p3.7) t rhdz t clcl - 5 t clcl - 5 ns movx ale low to input data valid (note 2) t lldv 2.5t clcl - 20 + t stc1 2.5t clcl - 20 + t stc1 ns port 0 address to valid data in (note 2) t avdv0 3t clcl - 20 + t stc1 3t clcl - 20 + t stc1 ns
ds89c420 ultra-high-speed microcontroller 6 of 47 1 cycle page mode 1 2 cycle page mode 1 4 cycle page mode 1 page mode 2 non-page mode parameter symbol min max min max min max min max min max units port 2 address to valid data in (note 2) t avdv2 t clcl - 16 + t stc1 1.5t clcl - 16 + t stc1 3.5t clcl - 16 + t stc1 3.0t clcl - 16 + t stc1 3.5t clcl - 20 + t stc1 ns ale low to rd or wr low (note 2) t llrl ( t llwl) 0.5t clcl - 8 + t stc2 0.5t clcl + 1 + t stc2 2t clcl - 8 + t stc2 2t clcl + 8 + t stc2 4t clcl - 8 + t stc2 4t clcl + 8 + t stc2 0.5t clcl - 8 + t stc2 0.5t clcl + 4 + t stc2 0.5t clcl - 8 + t stc2 0.5t clcl + 4 + t stc2 ns port 0 address valid to rd or wr low (note 2) t avrl0 ( t avwl0) 1.5t clcl - 5 + t stc2 t clcl - 5 + t stc2 ns port 2 address valid to rd or wr low (note 2) t avrl2 (t avwl2) 0 + t stc5 - 5 0.5t clcl - 5 + t stc5 1.5t clcl - 5 + t stc5 t clcl - 5 + t stc5 1.5t clcl - 5 + t stc5 ns data out valid to wr transition (note 1) t qvwx -5 -5 -5 -5 -5 ns data hold after wr (note 1) t whqx 20 20 20 20 20 ns rd or wr high to ale high (note 1) t rhlh ( t whlh) t stc2 - 2 t stc2 + 6 t stc2 - 2 t stc2 + 6 t stc2 - 2 t stc2 + 6 t stc2 - 2 t stc2 + 6 t stc2 - 2 t stc2 + 6 ns * specifications to -40c are guaranteed by design and not production tested.
ds89c420 ultra-high-speed microcontroller 7 of 47 note 1: the clock divide and crystal multiplier control bits in the pmr register determine the system clock frequency and the minimum/ maximum external clock speed. the term ?1/t clcl ? used in the ac characteristics variable timing table is determined from the following table. the minimum/maximum external clock speed columns clarify that [(external clock speed) x (multipliers)] cannot exceed the rated speed of the device. in addition, the use of the crystal multiplier feature establishes a minimum external spe ed. external clock speed 4x/ 2x cd1 cd0 number of external clock cycles per system clock (1/t clcl ) min max 1 0 0 1/4 5mhz 8.25mhz 0 0 0 1/2 10mhz 16.5mhz x 0 1 reserved ? ? x 1 0 1 see ac characteristics see ac characteristics x 1 1 1024 see ac characteristics see ac characteristics note 2: external movx instruction times are dependent on the setting of the md2, md1, and md0 bits in the clock control register. the t erms ?t stc1 , t stc2 , t stc3 ? used in the variable timing table are calculated through the use of the table given below. md2 md1 md0 movx instruction time (machine cycles) t stc1 (t clcl ) t stc2 ( t clcl ) t stc3 ( t clcl ) t stc4 ( t clcl ) t stc5 ( t clcl ) 0 0 0 2 0 0 0 0 0 0 0 1 3 2 1 0 0 1 0 1 0 4 6 1 0 0 1 0 1 1 5 10 1 0 0 1 1 0 0 9 14 5 4 1 1 1 0 1 10 18 5 4 1 1 1 1 0 11 22 5 4 1 1 1 1 1 12 26 5 4 1 1 note 3: maximum load capacitance (to meet the above timing) for port 0, ale, psen , wr , and rd is limited to 60pf. xtal1 and xtal2 load capacitance is dependent on the frequency of the selected crystal. figure 1. non-page mode timing ale port 0 port 2 lsb data xtal1 psen rd msb msb msb msb msb wr lsb lsb lsb lsb data movx movx opcode t clcl t avll2 t lhll t wlwh t llax2 t llwl t llpl t llax t lliv t aviv0 t pxix t plph t pliv t avll3 t llax3 t rlrh t plaz t whlh t whqx t qvwx t aviv2 t avdv2 t avwl2 t pxiz t avll t lldv t avdv0 t rhdx t rhdz t rldv t avwl0
ds89c420 ultra-high-speed microcontroller 8 of 47 figure 2. page-mode 1 timing ale port 0 port 2 lsb data xtal1 psen rd wr lsb lsb lsb data movx opcode t clcl t avll2 t lhll t rldv t wlwh t llax2 t llwl t llax t aviv2 t pxix t plph t pliv t avwl2 t llax3 t rlrh t whlh t whqx msb lsb msb msb msb lsb opcode movx t qvwx t avdv2 t rhdx figure 3. page-mode 2 timing ale port 0 port 2 msb opcode xtal1 psen rd wr msb msb lsb msb data movx movx t clcl t avll2 t lhll t wlwh t llax2 t llwl t llpl t lliv t aviv0 t pxix t pliv t avll3 t llax3 t plph t plaz t whlh t whqx t qvwx t aviv2 t avdv2 t avwl2 t pxiz t avll t lldv t avdv0 t rhdx t rhdz t rldv t avwl0 t llax lsb lsb lsb lsb lsb opcode data t rlrh
ds89c420 ultra-high-speed microcontroller 9 of 47 external clock characteristics (v cc = 4.5v to 5.5v; t a = -40c to +85c.)* parameter symbol min max units clock high time t chcx 10 ns clock low time t clcx 10 ns clock rise time t clch 5 ns clock fall time t chcl 5 ns serial port mode 0 timing characteristics (v cc = 4.5v to 5.5v; t a = -40c to +85c.)* ( figure 4 ) 33mhz variable parameter symbol conditions min max min max units sm2 = 0 360 12t clcl clock cycle time t xlxl sm2 = 1 120 4t clcl ns sm2 = 0 200 10t clcl - 100 output data setup to clock rising t qvxh sm2 = 1 40 3t clcl - 10 ns sm2 = 0 50 2t clcl - 10 output data hold to clock rising t xhqx sm2 = 1 20 t clcl - 100 ns sm2 = 0 0 0 input data hold after clock rising t xhdx sm2 = 1 0 0 ns sm2 = 0 200 10t clcl - 100 clock rising edge to input data valid t xhdv sm2 = 1 40 3t clcl - 50 ns note: sm2 is the serial port 0, mode bit 2. when serial port 0 is operating in mode 0 (sm0 = sm1 = 0), sm2 determines the number of crystal clocks in a serial-port clock cycle. * specifications to -40c are guaranteed by design and not production tested.
ds89c420 ultra-high-speed microcontroller 10 of 47 figure 4. serial port timing t xlxl t xhdv t xhdx t xhqx t qvxh transmit receive ale write to sbuf psen rxd data out txd clock txd clock r1 ti write to scon to clear ri rxd data in d0 di d3 d4 d2 d5 d6 d7 d7 d6 d5 d4 d3 d2 di d0 rxd data in txd clock r e c e i v e t r a n s m i t d0 di d6 d7 write to scon to clear ri r1 d0 di d6 d7 1/(xtal freq/12) ale psen write to sbuf rxd data out txd clock ti txd clock serial port (synchronous mode) sm2 = 0 tdx clock = xtal freq/12 serial port (synchronous mode) sm2 = 1 tdx clock = xtal freq/4
ds89c420 ultra-high-speed microcontroller 11 of 47 power cycle timing characteristics (v cc = 4.5v to 5.5v; t a = -40c to +85c.) (note 1) parameter symbol conditions min typ max units crystal startup time t csu (note 2) 8 ms power-on reset delay t por (note 3) 65,536 t clcl note 1: specifications to -40c are guaranteed by design and not production tested. note 2: startup time for a crystal varies with load capacitance and manufacturer. time shown is for a 11.0592mhz crystal manufactured by fox electronics. note 3: reset delay is a synchronous counter of crystal oscillations after crystal startup. counting begins when the level on the xtal 1 pin meets the v ih2 criteria. at 33mhz, this time is 1.99ms. flash memory programming characteristics (v cc = 4.5v to 5.5v; t a = +21c to +27c.) parameter symbol conditions min typ max units oscillator frequency 1 / t clcl 4 6 mhz address setup to prog low t avgl 48t clcl address hold after prog t ghax 48t clcl data setup to prog low t dvgl 48t clcl data hold after prog t ghdx 48t clcl prog pulse width t glgh 85 100 s address to data valid t avqv 48t clcl enable low to data valid t elqv 48t clcl data float after enable t ehqz 0 48t clcl prog high to prog low t ghgl 10 s
ds89c420 ultra-high-speed microcontroller 12 of 47 pin description pin dip plcc tqfp name function 40 12, 44 6, 38 v cc v cc - +5v 20 1, 22, 23, 34 16, 17, 28, 39 gnd logic ground 9 10 4 rst external reset. the rst input pin is bidirectional and contains a schmitt trigger to recognize external active-high reset inputs. the pin also employs an internal pulldown resistor to allow for a combination of wire-ored external reset sources. an rc is not required for power-up, since the device provides this function internally. 19 21 15 xtal1 18 20 14 xtal2 xtal1, xtal2. the crystal oscillator pins xtal1 and xtal2 provide support for fundamental mode parallel resonant, at cut crystals. xtal1 also acts as an input if there is an external clock source in place of a crystal. xtal2 serves as the output of the crystal amplifier. 29 32 26 psen program store enable. this signal is commonly connected to optional external program memory as a chip enable. psen provides an active-low pulse and is driven high when external program memory is not being accessed. in 1-cycle page mode 1, psen remains low for consecutive page hits. 30 33 27 ale/ prog address latch enable. functions as a clock to latch the external address lsb from the multiplexed address/data bus on port 0. this signal is commonly connected to the latch enable of an external 373 family transparent latch. in default mode, ale has a pulse width of 1.5 xtal1 cycles and a period of four xtal1 cycles. in page mode, the ale pulse width is altered according to the page mode selection. in traditional 8051 mode, ale is high when using the emi reduction mode and during a reset condition. ale can be enabled by writing aleon = 1 (pmr.2). note that ale operates independently of aleon during external memory accesses. as an alternate mode, this pin ( prog ) is used to execute the parallel program function. 39 43 37 p0.0 (ad0) 38 42 36 p0.1 (ad1) 37 41 35 p0.2 (ad2) 36 40 34 p0.3 (ad3) 35 39 33 p0.4 (ad4) 34 38 32 p0.5 (ad5) 33 37 31 p0.6 (ad6) 32 36 30 p0.7 (ad7) port 0 (ad0?7), i/o. port 0 is an open-drain 8-bit, bidirectional i/o port. as an alternate function, port 0 can function as the multiplexed address/data bus to access off-chip memory. during the time when ale is high, the lsb of a memory address is presented. when ale falls to a logic 0, the port transitions to a bidirectional data bus. this bus is used to read external program memory and read/write external ram or peripherals. when used as a memory bus, the port provides weak pullups for logic 1 outputs. the reset condition of port 0 is three-state. pullup resistors are required when using port 0 as an i/o port. 1?8 2?9 40?44, 1? 3 port 1, i/o. port 1 functions as both an 8-bit, bidirectional i/o port and an alternate functional interface for timer 2 i/o, new external interrupts, and new serial port 1. the reset condition of port 1 is with all bits at logic 1. in this state, a weak pullup holds the port high. this condition also serves as an input state, since any external circuit that writes to the port overcomes the weak pullup. when software writes a 0 to any port pin, the ds89c420 activates a strong pulldown that remains on until either a 1 is written or a reset occurs. writing a 1 after the port has been at 0 causes a strong transition driver to turn on, followed by a weaker sustaining pullup. once the momentary strong driver turns off, the port again becomes the output high (and input) state. the alternate functions of port 1 are outlined below. port alternate function 1 2 40 p1.0 t2 external i/o for timer/counter 2 2 3 41 p1.1 t2ex timer 2 capture/reload trigger 3 4 42 p1.2 rxd1 serial port 1 receive 4 5 43 p1.3 txd1 serial port 1 transmit 5 6 44 p1.4 int2 external interrupt 2 (positive edge detect) 6 7 1 p1.5 int3 external interrupt 3 (negative edge detect) 7 8 2 p1.6 int4 external interrupt 4 (positive edge detect) 8 9 3 p1.0?p1.7 p1.7 int5 external interrupt 5 (negative edge detect)
ds89c420 ultra-high-speed microcontroller 13 of 47 pin description (continued) pin dip plcc tqfp name function 21 24 18 p2.0 (a8) 22 25 19 p2.1 (a9) 23 26 20 p2.2 (a10) 24 27 21 p2.3 (a11) 25 28 22 p2.4 (a12) 26 29 23 p2.5 (a13) 27 30 24 p2.6 (a14) 28 31 25 p2.7 (a15) port 2 (a8?15), i/o. port 2 is an 8-bit, bidirectional i/o port. the reset condition of port 2 is logic high. in this state, a weak pullup holds the port high. this condition also serves as an input mode, since any external circuit that writes to the port overcomes the weak pullup. when software writes a 0 to any port pin, the ds89c420 activates a strong pulldown that remains on until either a 1 is written or a reset occurs. writing a 1 after the port has been at 0 causes a strong transition driver to turn on, followed by a weaker sustaining pullup. once the momentary strong driver turns off, the port again becomes both the output high and input state. as an alternate function, port 2 can function as the msb of the external address bus when reading external program memory and read/write external ram or peripherals. in page mode 1, port 2 provides both the msb and lsb of the external address bus; in page mode 2, it provides the msb and data. 10?17 11, 13?19 5, 7?13 p3.0?p3.7 port 3, i/o. port 3 functions as both an 8-bit, bidirectional i/o port and an alternate functional interface for external interrupts, serial port 0, timer 0 and 1 inputs, and rd and wr strobes. the reset condition of port 3 is with all bits at logic 1. in this state, a weak pullup holds the port high. this condition also serves as an input mode, since any external circuit that writes to the port overcomes the weak pullup. when software writes a 0 to any port pin, the ds89c420 activates a strong pulldown that remains on until either a 1 is written or a reset occurs. writing a 1 after the port has been at 0 causes a strong transition driver to turn on, followed by a weaker sustaining pullup. once the momentary strong driver turns off, the port again becomes both the output high and input state. the alternate modes of port 3 are outlined below. port alternate function 10 11 5 p3.0 p3.0 rxd0 serial port 0 receive 11 13 7 p3.1 p3.1 txd0 serial port 0 transmit 12 14 8 p3.2 p3.2 int0 external interrupt 0 13 15 9 p3.3 p3.3 int1 external interrupt 1 14 16 10 p3.4 p3.4 t0 timer 0 external input 15 17 11 p3.5 p3.5 t1 timer 1 external input 16 18 12 p3.6 p3.6 wr external data memory write strobe 17 19 13 p3.7 p3.7 rd external data memory read strobe 31 35 29 ea external access. allows selection of internal or external program memory. connect to ground to force the ds89c420 to use an external memory- program memory. the internal ram is still accessible as determined by register settings. connect to v cc to use internal flash memory.
ds89c420 ultra-high-speed microcontroller 14 of 47 figure 5. block diagram control & sequencer internal registers decoder ir interrupt cpu serial i/o timer / counters 1kx 8 ram 16k x 8 flash i/o ports sfrs dptr dptr1 sp pc ar inc ar watchdog timer & power manager clock & reset memory control rom loader x t a l 2 x t a l 1 r s t p s e n e a a l e / p r o g p0 p1 p2 p3 address bus internal control bus detailed description the ds89c420 is pin compatible with all three packages of the standard 8051 and includes standard resources such as three timer/counters, four 8-bit i/o ports, and a serial port. it features 16kb of in-system programmable flash memory, which can be programmed in-system from an i/o port using a built-in program memory loader. it can also be loaded externally using standard commercially available programmers. besides greater speed, the ds89c420 includes 1kb of data ram, a second full-hardware serial port, seven additional interrupts, two more levels of interrupt priority, programmable watchdog timer, brownout monitor, and power-fail reset. the device also provides dual data pointers (dptrs) to speed up block-data memory moves. this feature is further enhanced with a new selectable automatic increment/decrement and toggle-select operation. the speed of movx data memory access can be adjusted by adding stretch values up to 10 machine cycle times for flexibility in selecting external memory and peripherals. a power management mode (pmm) significantly consumes less power by slowing the cpu execution rate from 1 clock period per cycle to 1024 clock periods per cycle. a selectable switchback feature can automatically cancel this mode to enable a normal speed response to interrupts. the emi reduction feature disables the ale signal when the processor is not accessing external memory. dallas semiconductor ds89c420
ds89c420 ultra-high-speed microcontroller 15 of 47 compatibility the ds89c420 is a fully static cmos 8051-compatible microcontroller similar to the ds87c520 in functional features, but with much higher performance. in most cases the ds89c420 can drop into an existing socket for the 8xc51 family to improve the operation significantly. while remaining familiar to 8051 family users, it has many new features. the ds89c420 runs the standard 8051 family instruction set and is pin compatible with dip, plcc, and tqfp packages. in general, software written for existing 8051-based systems works without ds89c420 modification, with the exception of critical timing routines, since the ds89c420 performs its instructions much faster than the original for any given crystal selection. the ds89c420 provides three 16-bit timer/counters, two full-duplex serial ports, and 256 bytes of direct ram plus 1kb of extra movx ram. i/o ports can operate as in standard 8051 products. timers default to a 12 clock-per- cycle operation to keep their timing compatible with original 8051 family systems. however, timers are individually programmable to run at the new 1 clock-per-cycle if desired. the ds89c420 provides several new hardware features implemented by new sfrs. performance overview the ds89c420 features a completely redesigned high-speed 8051-compatible core and allows operation at a higher clock frequency, but the updated core does not have the dummy memory cycles that are present in a standard 8051. a conventional 8051 generates machine cycles using the clock frequency divided by 12. in the ds89c420, the same machine cycle takes 1 clock. thus, the fastest instructions execute 12 times faster for the same crystal frequency (and actually 24 times faster for the inc data pointer instruction). it should be noted that this speed improvement reduces when using external memory access modes that require more than 1 clock per cycle. improvement of individual programs depends on the actual instructions used. speed-sensitive applications make the most use of instructions that are 12 times faster. however, the sheer number of 12-to-1 improved op codes makes dramatic speed improvements likely for any code. these architecture improvements produce instruction cycle times as low as 30ns (33mips). the dual data pointer feature also allows the user to eliminate wasted instructions when moving blocks of memory. the new page modes allow for increased efficiency in external memory accesses. instruction set summary all instructions perform the same functions as their 8051 counterparts. their effect on bits, flags, and other status functions is also identical. however, the timing of each instruction is different in both absolute and relative number of clocks. for absolute timing of real-time events, the timing of software loops can be calculated using information in the ?instruction set? table of the ultra-high-speed flash microcontroller user?s guide . however, counter/timers default to run at the older 12 clocks per increment. in this way, timer-based events occur at the standard intervals with software executing at higher speed. timers optionally can run at lower numbers of clocks per increment to take advantage of faster processor operation. the relative time of some instructions might be different in the new architecture than it was previously. for example, in the original architecture, the ?movx a, @dptr? instruction and the ?mov direct, direct? instruction used two machine cycles or 24 oscillator cycles. therefore, they required the same amount of time. in the ds89c420, the movx instruction takes as little as two machine cycles or two oscillator cycles but the ?mov direct, direct? uses three machine cycles or three oscillator cycles. while both are faster than their original counterparts, they now have different execution times. this is because the ds89c420 usually uses one machine cycle for each instruction byte and requires one cycle for execution. the user concerned with precise program timing should examine the timing of each instruction to become familiar with the changes. special function registers (sfrs) all peripherals and operations that are not explicit instructions in the ds89c420 are controlled through sfrs. the most common features basic to the architecture are mapped to the sfrs. these include the cpu registers (acc, b, and psw), data pointers (dptrs), stack pointer, i/o ports, timer/counters, and serial ports. in many cases, an sfr controls an individual function or reports the function?s status. the sfrs reside in register locations 80h?ffh and are only accessible by direct addressing. sfrs whose addresses end in 0h or 8h are bit-addressable.
ds89c420 ultra-high-speed microcontroller 16 of 47 all standard sfr locations from the 8051 are duplicated in the ds89c420 and several sfrs have been added for the unique features of the ds89c420. most of these features are controlled by bits in sfrs located in unused locations in the 8051 sfr map. this allows for increased functionality while maintaining complete instruction set compatibility. table 1 summarizes the sfrs and their locations. table 2 specifies the default reset condition for all sfr bits. data pointers the data pointers (dptr and dptr1) are used to assign a memory address for the movx instructions. this address can point to a movx ram location (on-chip or off-chip), or a memory-mapped peripheral. two pointers are useful when moving data from one memory area to another, or when using a memory-mapped peripheral for both source and destination addresses. the user selects the active pointer through a dedicated sfr bit (sel = dps.0), or activates an automatic toggling feature for altering the pointer selection (tsl = dps.5). an additional feature, if selected, provides automatic incrementing or decrementing of the current dptr. stack pointer the stack pointer denotes the register location at the top of the stack, which is the last used value. the user can place the stack anywhere in the scratchpad ram by setting the stack pointer to the desired location, although the lower bytes are normally used for working registers. i/o ports the ds89c420 offers four 8-bit i/o ports. each i/o port is represented by an sfr location, and can be written or read. the i/o port has a latch that contains the value written by software. counter/timers three 16-bit timer/counters are available in the ds89c420. each timer is contained in two sfr locations that can be read or written by software. the timers are controlled by other sfrs described in the ?sfr bit description? section of the ultra-high-speed flash microcontroller user?s guide . serial ports the ds89c420 provides two uarts that are controlled and accessed by sfrs. each uart has an address that is used to read and write the uart. the same address is used for read and write operations, which are distinguished by the instruction. its own sfr control register controls each uart.
ds89c420 ultra-high-speed microcontroller 17 of 47 table 1. special function registers register addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p0 80h p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 sp 81h ? ? ? ? ? ? ? ? dpl 82h ? ? ? ? ? ? ? ? dph 83h ? ? ? ? ? ? ? ? dpl1 84h ? ? ? ? ? ? ? ? dph1 85h ? ? ? ? ? ? ? ? dps 86h id1 id0 tsl aid ? ? ? sel pcon 87h smod_0 smod0 ofdf ofde gf1 gf0 stop idle tcon 88h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 tmod 89h gate c/ t m1 m0 gate c/ t m1 m0 tl0 8ah ? ? ? ? ? ? ? ? tl1 8bh ? ? ? ? ? ? ? ? th0 8ch ? ? ? ? ? ? ? ? th1 8dh ? ? ? ? ? ? ? ? ckcon 8eh wd1 wd0 t2m t1m t0m md2 md1 md0 p1 90h p1.7/ int5 p1.6/int4 p1.5/ int3 p1.4/int2 p1.3/txd1 p1.2/rxd1 p1.1/t2ex p1.0/t2 exif 91h ie5 ie4 ie3 ie2 ckry rgmd rgsl bgs ckmod 96h ? ? t2mh t1mh t0mh ? ? ? scon0 98h sm0/fe_0 sm1_0 sm2_0 ren_0 tb8_0 rb8_0 ti_0 ri_0 sbuf0 99h ? ? ? ? ? ? ? ? acon 9dh pagee pages1 pages0 ? ? ? ? ? p2 a0h p2.7 p2.6 p2.5 p2.4 p2.3 p2.2 p2.1 p2.0 ie a8h ea es1 et2 es0 et1 ex1 et0 ex0 saddr0 a9h ? ? ? ? ? ? ? ? saddr1 aah ? ? ? ? ? ? ? ? p3 b0h p3.7/ rd p3.6/ wr p3.5/t1 p3.4/t0 p3.3/ int1 p3.2/ int0 p3.1/txd0 p3.0/rxd0 ip1 b1h ? mps1 mpt2 mps0 mpt1 mpx1 mpt0 mpx0 ip0 b8h ? lps1 lpt2 lps0 lpt1 lpx1 lpt0 lpx0 saden0 b9h ? ? ? ? ? ? ? ? saden1 bah ? ? ? ? ? ? ? ? scon1 c0h sm0/fe_1 sm1_1 sm2_1 ren_1 tb8_1 rb8_1 ti_1 ri_1 sbuf1 c1h ? ? ? ? ? ? ? ? romsize c2h ? ? ? ? prame rms2 rms1 rms0 pmr c4h cd1 cd0 swb ctm 4x/ 2x aleon dme1 dme0 status c5h pis2 pis1 pis0 ? spta1 spra1 spta0 spra0 ta c7h ? ? ? ? ? ? ? ? t2con c8h tf2 exf2 rclk tclk exen2 tr2 c/ t2 cp/ rl2 t2mod c9h ? ? ? ? ? ? t2oe dcen rcap2l cah ? ? ? ? ? ? ? ? rcap2h cbh ? ? ? ? ? ? ? ? tl2 cch ? ? ? ? ? ? ? ? th2 cdh ? ? ? ? ? ? ? ? psw d0h cy ac f0 rs1 rs0 ov f1 p fcntl d5h fbusy ferr ? ? fc3 fc2 fc1 fc0 fdata d6h ? ? ? ? ? ? ? ? wdcon d8h smod_1 por epfi pfi wdif wtrf ewt rwt acc e0h ? ? ? ? ? ? ? ? eie e8h ? ? ? ewdi ex5 ex4 ex3 ex2 b f0h ? ? ? ? ? ? ? ? eip1 f1h ? ? ? mpwdi mpx5 mpx4 mpx3 mpx2 eip0 f8h ? ? ? lpwdi lpx5 lpx4 lpx3 lpx2
ds89c420 ultra-high-speed microcontroller 18 of 47 table 2. sfr reset value register addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p0 80h 1 1 1 1 1 1 1 1 sp 81h 0 0 0 0 0 1 1 1 dpl 82h 0 0 0 0 0 0 0 0 dph 83h 0 0 0 0 0 0 0 0 dpl1 84h 0 0 0 0 0 0 0 0 dph1 85h 0 0 0 0 0 0 0 0 dps 86h 0 0 0 0 0 1 0 0 pcon 87h 0 0 special special 0 0 0 0 tcon 88h 0 0 0 0 0 0 0 0 tmod 89h 0 0 0 0 0 0 0 0 tl0 8ah 0 0 0 0 0 0 0 0 tl1 8bh 0 0 0 0 0 0 0 0 th0 8ch 0 0 0 0 0 0 0 0 th1 8dh 0 0 0 0 0 0 0 0 ckcon 8eh 0 0 0 0 0 0 0 1 p1 90h 1 1 1 1 1 1 1 1 exif 91h 0 0 0 0 special special special 0 ckmod 96h 1 1 0 0 0 1 1 1 scon0 98h 0 0 0 0 0 0 0 0 sbuf0 99h 0 0 0 0 0 0 0 0 acon 9dh 0 0 0 1 1 1 1 1 p2 a0h 1 1 1 1 1 1 1 1 ie a8h 0 0 0 0 0 0 0 0 saddr0 a9h 0 0 0 0 0 0 0 0 saddr1 aah 0 0 0 0 0 0 0 0 p3 b0h 1 1 1 1 1 1 1 1 ip1 b1h 1 0 0 0 0 0 0 0 ip0 b8h 1 0 0 0 0 0 0 0 saden0 b9h 0 0 0 0 0 0 0 0 saden1 bah 0 0 0 0 0 0 0 0 scon1 c0h 0 0 0 0 0 0 0 0 sbuf1 c1h 0 0 0 0 0 0 0 0 romsize c2h 1 1 1 1 0 1 0 1 pmr c4h 1 0 0 0 0 0 0 0 status c5h 0 0 0 1 0 0 0 0 ta c7h 1 1 1 1 1 1 1 1 t2con c8h 0 0 0 0 0 0 0 0 t2mod c9h 1 1 1 1 1 1 0 0 rcap2l cah 0 0 0 0 0 0 0 0 rcap2h cbh 0 0 0 0 0 0 0 0 tl2 cch 0 0 0 0 0 0 0 0 th2 cdh 0 0 0 0 0 0 0 0 psw d0h 0 0 0 0 0 0 0 0 fcntl d5h 1 0 1 1 0 0 0 0 fdata d6h 0 0 0 0 0 0 0 0 wdcon d8h 0 special 0 special 0 special special 0 acc e0h 0 0 0 0 0 0 0 0 eie e8h 1 1 1 0 0 0 0 0 b f0h 0 0 0 0 0 0 0 0 eip1 f1h 1 1 1 0 0 0 0 0 eip0 f8h 1 1 1 0 0 0 0 0 memory organization there are three distinct memory areas in the ds89c420: scratchpad registers, program memory, and data memory. all registers are located on-chip but the program and data memory spaces can either be on-chip, off-chip, or both. there are 16kb of on-chip program memory implemented in flash memory and 1kb of on-chip data memory space that can be configured as program space using the prame bit in the romsize feature. the ds89c420 uses a memory-addressing scheme that separates program memory from data memory. the program and data segments can be overlapped since they are accessed in different ways. if the maximum address of on- chip program or data memory is exceeded, the ds89c420 performs an external memory access using the expanded memory bus. the psen signal goes active-low to serve as a chip enable or output enable when performing a code fetch from external program memory. movx instructions activate the rd or wr signal for
ds89c420 ultra-high-speed microcontroller 19 of 47 external movx data memory access. the lower 128 bytes of on-chip flash memory store reset and interrupt vectors. the program memory romsize feature allows software to dynamically configure the maximum address of on-chip program memory. this allows the ds89c420 to act as a bootloader for an external flash or nv sram. it also enables the use of the overlapping external program spaces. 256 bytes of on-chip ram serve as a register area and program stack, which are separated from the data memory. register space registers are located in the 256 bytes of on-chip ram, which can be divided into two subareas of 128 bytes each as illustrated in figure 6 . separate classes of instructions are used to access the registers and the program/data memory. the upper 128 bytes are overlapped with the 128 bytes of sfrs in the memory map. indirect addressing accesses the upper 128 bytes of scratchpad ram, and direct addressing accesses the sfr area. direct or indirect addressing can access the lower 128 bytes. there are four banks of eight individual working registers in the lower 128 bytes of scratchpad ram. the working registers are general-purpose ram locations that can be addressed within the selected bank by any instructions that use r0?r7. the register bank selection is controlled through the program status register in the sfr area. the contents of the working registers can be used for indirectly addressing the upper 128 bytes of scratchpad ram. to support the boolean operations, there are individually addressable bits in both the ram and sfr areas. in the scratchpad ram area, registers 20h?2fh are bit-addressable by software using boolean operation instructions. another use of the scratchpad ram area is for the stack. the stack pointer in the sfrs is used to select storage locations for program variables and for return addresses of control operations. memory configuration as illustrated in figure 6 , the ds89c420 incorporates two 8kb flash memories for on-chip program memory and 1kb of sram for on-chip data memory or a particular range (400?7ff) of ?alternate? program memory space. the ds89c420 uses an address scheme that separates program memory from data memory, such that the 16-bit address bus can address each memory area up to 64kb. program memory access on-chip program memory begins at address 0000h and is contiguous through 3fffh (16kb). exceeding the maximum address of on-chip program memory causes the device to access off-chip memory. however, the maximum on-chip decoded address is selectable by software using the romsize feature. software can cause the ds89c420 to behave like a device with less on-chip memory. this is beneficial when overlapping external memory is used. the maximum memory size is dynamically variable. thus, a portion of memory can be removed from the memory map to access off-chip memory, then be restored to access on-chip memory. in fact, all of the on-chip memory can be removed from the memory map allowing the full 64kb memory space to be addressed from off-chip memory. program memory addresses that are larger than the selected maximum are automatically fetched from outside the part through ports 0 and 2 ( figure 6 ). the romsize register is used to select the maximum on-chip decoded address for program memory. bits rms2, rms1, rms0 have the following effect: rms2 rms1 rms0 address maximum on-chip program memory 0 0 0 0k 0 0 1 1k/03ffh 0 1 0 2k/07ffh 0 1 1 4k/0fffh 1 0 0 8k/1fffh 1 0 1 16k (default)/3fffh 1 1 0 invalid?reserved 1 1 1 invalid?reserved
ds89c420 ultra-high-speed microcontroller 20 of 47 figure 6. memory map external data memory 8k x 8 flash memory (program) 1k x 8 sram data or prog mem addr from 400 - 7ff 128 bytes indirect addressing bit addressable bank 3 bank 2 bank 1 bank 0 00 1f 20 2f 7f 80 128 bytes sfr ff 0000 1fff 2000 3fff internal memory 03ff 0000 ffff ffff 4000 0000 0000 03ff external program memory internal registers 8k x 8 flash memory (program) the reset default condition is a maximum on-chip program-memory address of 16kb. when accessing external program memory, the first 16kb would be inaccessible. to select a smaller effective program memory size, software must alter bits rms2?rms0. altering these bits requires a timed access procedure as explained later. care should be taken so that changing the romsize register does not corrupt program execution. for example, assume that a ds89c420 is executing instructions from internal program memory near the 12kb boundary (~3000h) and that the romsize register is currently configured for a 16kb internal program space. if software reconfigures the romsize register to 4kb (0000h?0fffh) in the current state, the device immediately jumps to external program execution because program code from 4kb to 16kb (1000h?3fffh) is no longer located on-chip. this could result in code misalignment and execution of an invalid instruction. the recommended method is to modify the romsize register from a location in memory that is internal (or external) both before and after the operation. in the above example, the instruction that modifies the romsize register should be located below the
ds89c420 ultra-high-speed microcontroller 21 of 47 4kb (1000h) boundary or above the 16kb (3fffh) boundary so that it is unaffected by the memory modification. the same precaution should be applied if the internal program memory size is modified while executing from external program memory. for non-page mode operations, off-chip memory is accessed using the multiplexed address/data bus on p0 and the msb address on p2. while serving as a memory bus, these pins are not i/o ports. this convention follows the standard 8051 method of expanding on-chip memory. off-chip program memory access also occurs if the ea pin is logic 0. ea overrides all bit settings. the psen signal goes active (low) to serve as a chip enable or output enable when port 0 and port 2 fetch from external program memory. the rd and wr signals are used to control the external data memory device. data memory is accessed by movx instructions. the movx@ri instruction uses the value in the designated working register to provide the lsb of the address, while port 2 supplies the address msb. the movx@dptr instruction uses one of the two data pointers to move data over the entire 64kb external data memory space. software selects the data pointer to be used by writing to the sel bit (dps.0). the ds89c420 also provides a user option for high-speed external memory access by reconfiguring the external memory interface into page mode operation. note: when using the original 8051 expanded bus structure, the throughput is reduced by 75% compared with that of internal operations. this is due to the cpu being stalled for three out of four clocks waiting for the data fetch, which takes four clocks. page mode 1 is the only external addressing mode where the cpu does not require stalls for external memory access, but page misses result in reduced external access performance. on-chip program memory the processor can fetch the full on-chip program memory range automatically. the reset routines and all interrupt vectors are located in the lower 128 bytes of the on-chip program memory area. on-chip program memory is logically divided into two 8kb flash memory banks and is designed to be programmed with the standard 5v v cc supply by using a built-in program memory loader. it can also be programmed in standard flash or eprom programmers. the ds89c420 incorporates a memory management unit (mmu) and other hardware to support any of the two programming methods. the mmu controls program and data memory access, and provides sequencing and timing controls for programming the on-chip program memory. there is also a separate security flash block that is used to support a standard three-level lock, a 64-byte encryption array, and other flash options. security features the ds89c420 incorporates a 64-byte encryption array, allowing the user to verify program codes while viewing the data in encrypted form. the encryption array is implemented in a security flash memory block that has the same electrical and timing characteristics as the on-chip program memory. once the encryption array is programmed to non-ffh, the data presented in the verify mode is encrypted. each byte of data is xnored with a byte in the encryption array during verification. a three-level lock restricts viewing of the internal program and data memory contents. by programming the three lock bits, the user can select a level of security as specified in table 3 . once a security level is selected and programmed, the setting of the lock bits remains. only a mass erase can erase these bits to allow reprogramming the security level to a less restricted protection.
ds89c420 ultra-high-speed microcontroller 22 of 47 table 3. flash memory lock bits level lb1 lb2 lb3 protection 1 1 1 1 no program lock. encrypted verify if encryption array is programmed. 2 0 1 1 prevent movc in external memory from reading program code in internal memory. ea is sampled and latched on reset. allow no further parallel or program memory loader programming. 3 x 0 1 level 2 plus no verify operation. also prevent movx in external memory from reading internal sram. 4 x x 0 level 3 plus no external execution. the ds89c420 provides user-selectable options that must be set before beginning software execution. the option control register uses flash bits rather than sfrs, and is individually erasable and programmable as a byte-wide register. bit 3 of this register is defined as the watchdog por default. setting this bit to 1 disables the watchdog- reset function on power-up, and clearing this bit to 0 enables the watchdog-reset function automatically. other bits of this register are undefined and are at logic 1 when read. the value of this register can be read at address fch in parallel programming mode or when executing a verify-option control-register instruction in rom loader mode. the signature bytes can be read in rom loader mode or in parallel programming mode. reading data from addresses 30h, 31h, and 60h provides signature information about manufacturer, part, and extension as follows: address value function 30h dah manufacturer id 31h 42h ds89c420 device id 60h 01h device extension rom loader the full 16kb of on-chip flash program-memory space, security flash block, and external sram can be programmed in-system from an external source through serial port 0 under the control of a built-in rom loader. the rom loader also has an auto-baud feature that determines which baud rate frequencies are being used for communication and sets up the baud rate generator for communication at that frequency. when the ds89c420 is powered up and has entered its user operating mode, the rom loader mode can be invoked at any time by forcing rst = 1, ea = 0, and psen = 0. it remains in effect until power-down or when the condition (rst = 1 and psen = ea = 0) is removed. entering the rom loader mode forces the processor to start fetching from the 2kb internal rom for program memory initialization and other loader functions. the read/write accessibility is determined by the state of the lock bits, which can be verified directly by the rom loader. in the rom loader mode, a mass-erase operation also erases the memory bank select and sets it to the default state. otherwise, the memory bank select cannot be altered in the rom loader mode. the flash memory can be programmed (by the built-in rom loader) using commands that are received over the serial interface from a host pc. full details of the rom loader commands are given in the ultra-high-speed flash microcontroller user?s guide . host software to communicate with the rom loader is available in windows format as well as other platforms. contact our technical support department at micro.support@dalsemi.com for more information.
ds89c420 ultra-high-speed microcontroller 23 of 47 figure 7. interfacing the bootloader to a pc parallel programming the microcontroller also supports a programming mode such as that used by commercial device programmers. this mode is of little utility in normal applications and is only used by commercial device programmers. for information on this mode, contact our technical support department at micro.support@dalsemi.com . on-chip movx data memory on-chip data memory is provided by the 1kb sram and occupies addresses 0000h through 03ffh. the internal data memory is disabled after a power-on reset, and any movx instruction directs the data memory access to the external data memory. to enable the internal data memory, software must configure the data memory enable bits dme1 and dme0 (pmr.1-0). see ?sfr bit descriptions? in the ultra-high-speed flash microcontroller user?s guide for data memory configurations. once enabled, movx instructions with addresses inside the 1k range access the on-chip data memory, and addresses exceeding the 1k range automatically access external data memory. an internal data memory cycle spans only one system clock period to support fast internal execution.
ds89c420 ultra-high-speed microcontroller 24 of 47 table 4. parallel programming instruction set instruction p2.5:0, p1.7:0 p0.7:0 prog p2.6 p2.7 p3.6 p3.7 operation mass erase don?t care don?t care pl (1) h l l l mass erase the 16k x 8 program memory, the security block and the bank select. the contents of every memory location is returned to ffh. write program memory addr din pl (3) l h h h program the 16k program memory. read program memory addr dout h (4) l l h h verify the 16k program memory. write encryption array addr din pl (3) l h l h program the 64 byte encryption array. write lb1 don?t care don?t care pl (3) h h h h program lb1 to logic 0. write lb2 don?t care don?t care pl (3) h h l l program lb2 and lb1 to 00b. write lb3 don?t care don?t care pl (3) h l h l program lb3, lb2, and lb1 to 000b. read lock bits don?t care dout h (4) l l l h verify the lock bits. the lock bits are at address 40h and the three lsbs of the dout are the logic value of the lock bits lb3, lb2, and lb1, respectively. write option control register don?t care din pl (3) l h l l program the option control register. bit 3 of the din represents the watchdog por default setting. erase option control register don?t care don?t care pl (2) h l l h erase the option control register. this operation disables the watch-dog reset function on power-up. read address 30, 31, 60, fc addr dout h (4) l l l l 30h = manufacturer id 31h = device id 60h = device extension fch = verify the option control register. bit 3 of the dout is the logic value of the watchdog por. 1) mass erase requires an active-low prog pulse width of 828ms. 2) erase option control register requires an active-low prog pulse width of 828ms. 3) byte program requires an active-low prog pulse width of 100 s max. 4) prog is weakly pulled to a high internally. note 1: p3.2 is pulled low during programming to indicate busy. p3.2 is pulled high again when programming is completed to indicate re ady. note 2: p3.0 is pulled high during programming to indicate an error. data pointer increment/decrement and options the ds89c420 incorporates a hardware feature to assist applications that require data pointer increment/decrement. data pointer increment/decrement bits id0 and id1 (dps.6 and dps.7) define how the inc dptr instruction functions in relation to the active dptr (selected by the sel bit). setting id0 = 1 and sel = 0 enables the decrement operation for dptr, and execution of the inc dptr instruction decrements the dptr contents by 1. similarly, setting id1 = 1 and sel = 1 enables the decrement operation for dptr1, and execution of the inc dptr instruction decrements the dptr1 contents by 1. with this feature, the user can configure the data pointers to operate in four ways for the inc dptr instruction: id1 id0 sel = 0 sel = 1 0 0 increment dptr increment dptr1 0 1 decrement dptr increment dptr1 1 0 increment dptr decrement dptr1 1 1 decrement dptr decrement dptr1
ds89c420 ultra-high-speed microcontroller 25 of 47 the sel (dps.0) bit always selects the active data pointer. the ds89c420 offers a programmable option that allows any instructions related to data pointer to toggle the sel bit automatically. this option is enabled by setting the toggle-select-enable bit (tsl-dps.5) to logic 1. once enabled, the sel bit is automatically toggled after the execution of one of the following five dptr-related instructions: inc dptr mov dptr #data16 movc a, @a+dptr movx a, @dptr movx @dptr, a the ds89c420 also offers a programmable option that automatically increases (or decreases) the contents of the selected data pointer by 1 after the execution of a dptr-related instruction. the actual function (increment or decrement) is dependent upon the setting of the id1 and id0 bits. this option is enabled by setting the automatic increment/decrement enable (aid-dps.4) to a logic 1 and is affected by one of the following three instructions: movc a, @a+dptr movx a, @dptr movx @dptr, a external memory the ds89c420 executes external memory cycles for code fetches and read/writes of external program and data memory. a non-page external memory cycle is four times slower than the internal memory cycles (i.e., an external memory cycle contains four system clocks). for this reason, although a ds89c420 can be substituted for a rom- less 8051 device (ds80c310, c320, etc.), there is no increase in execution speed. however, a page mode external memory cycle can be completed in 1, 2, or 4 system clocks for a page hit and 2, 4, or 8 system clocks for a page miss, depending on user selection. the ds89c420 also supports a second page mode operation with a different external bus structure that provides for fast external code fetches but uses 4 system clock cycles for data memory access. external program memory interface (non-page mode) figure 8 shows the timing relationship for internal and external code fetches when cd1 and cd0 are set to 10b, assuming the microcontroller is in non-page mode for external fetches. note that an external program fetch takes 4 system clocks, and an internal program fetch requires only 1 system clock. as illustrated in figure 8, ale is deasserted when executing an internal memory fetch. the ds89c420 provides a programmable user option to turn on ale during internal program memory operation. ale is automatically enabled for code fetch externally, independent of the setting of this option. psen is only asserted for external code fetches, and is inactive during internal execution. external data memory interface in non-page mode operation just like the program memory cycle, the external data memory cycle is four times slower than the internal data memory cycle in non-page mode. a basic internal memory cycle contains one system clock and a basic external memory cycle contains four system clocks for non-page mode operation. the ds89c420 allows software to adjust the speed of external data memory access by stretching the memory bus cycle. ckcon (8eh) provides an application-selectable stretch value for this purpose. software can change the stretch value dynamically by changing the setting of ckcon.2?ckcon.0. table 5 shows the data memory cycle stretch values and their effects on the external movx-memory bus cycle and the control signal pulse width in terms of the number of oscillator clocks. a stretch machine cycle always contains four system clocks.
ds89c420 ultra-high-speed microcontroller 26 of 47 figure 8. external program memory access (non-page mode and cd1:cd0 = 10) internal memory cycles c2 c3 c4 c1 c2 c3 c4 xtal1 ale port 0 port 2 psen c1 ext memory cycle ext memory cycle msb add msb add lsb add data lsb add data table 5. data memory cycle stretch values rd / wr pulse width (in number of oscillator clocks) md2:md0 stretch cycles 4x/ 2x , cd1, cd0 = 100 4x/ 2x , cd1, cd0 = 000 4x/ 2x , cd1, cd0 = x10 4x/ 2x , cd1, cd0 = x11 000 0 0.5 1 2 2048 001 1 1 2 4 4096 010 2 2 4 8 8192 011 3 3 6 12 12288 100 7 4 8 16 16384 101 8 5 10 20 20480 110 9 6 12 24 24576 111 10 7 14 28 28672 as shown in table 5 , the stretch feature supports eight stretched external data-memory access cycles that can be categorized into three timing groups. when the stretch value is cleared to 000b, there is no stretch on external data memory access and a movx instruction is completed in two basic memory cycles. when the stretch value is set to 1, 2, or 3, the external data-memory access is extended by 1, 2, or 3 stretch machine cycles, respectively. note that the first stretch value does not result in adding four system clocks to the rd / wr control signals. this is because the first stretch uses one system clock to create additional setup time and one system clock to create additional address hold time. when using very slow ram and peripherals, a larger stretch value (4?7) can be selected. in this stretch category, one stretch machine cycle (4 system clocks) is used to stretch the ale pulse width, one stretch machine cycle is used to create additional setup, one stretch machine cycle is used to create additional hold time, and one stretch machine cycle is added to the rd or wr strobes. figure 9 and figure 10 illustrate the timing relationship for external data-memory access in full speed (stretch value = 0), in the default stretch setting (stretch value = 1), and slow data-memory accessing (stretch value = 4) when the system clock is in divide by one mode (cd1:cd0 = 10b).
ds89c420 ultra-high-speed microcontroller 27 of 47 figure 9. non-page mode, external data-memory access (stretch = 0, cd1:cd2 = 10) ale port 0 xtal1 psen rd wr movx inst a data a a a a port 2 movx instruction 1st machine cycle 2nd machine cycle movx instruction fetch memory access stretch = 0 figure 10. non-page mode, external data-memory access (stretch = 1, cd1:cd2 = 10) ale port 0 xtal1 psen rd wr movx inst a data a a a a port 2 movx instruction 1st machine cycle 2nd machine cycle movx instruction fetch memory access stretch = 1 3rd machine cycle
ds89c420 ultra-high-speed microcontroller 28 of 47 page mode, external memory cycle page mode retains the basic circuitry requirement for original 8051 external memory interface, but alters the configuration of p0 and p2 for the purposes of address output and data i/o during external memory cycles. additionally, the functions of ale and psen are altered to support this mode of operation. setting the pagee (acon.7) bit to logic 1 enables page mode. clearing the pagee bit to a logic 0 disables the page mode and the external bus structure defaults to the original 8051 expanded bus configuration (non-page mode). the ds89c420 supports page mode in two external bus structures. the logic value of the page mode select bits in the acon register determines the external bus structure and the basic memory cycle in the number of system clocks. table 6 summarizes this option. the first three selections use the same bus structure but with a different memory cycle time. setting the select bits to 11b selects another bus structure. write access to the acon register requires a timed access. table 6. page mode select clocks per memory cycle pages1:pages0 page hit page miss external bus structure 00 1 2 p0: primary data bus. p2: primary address bus, multiplexing both the upper byte and lower byte of the address. 01 2 4 p0: primary data bus. p2: primary address bus, multiplexing both the upper byte and lower byte of the address. 10 4 8 p0: primary data bus. p2: primary address bus, multiplexing both the upper byte and lower byte of the address. 11 2 4 p0: lower address byte. p2: the upper address byte is multiplexed with the data byte. note: this setting affects external code fetches only; accessing the external data memory requires 4 clock cycles, regardless of page hit or miss. the first page mode (page mode 1) external bus structure uses p2 as the primary address bus, (multiplexing both the most significant byte (msb) and least significant byte (lsb) of the address for each external memory cycle) and p0 is used as the primary data bus. during external code fetches, p0 is held in a high-impedance state by the processor. op codes are driven by the external memory onto p0 and latched at the end of the external fetch cycle at the rising edge of psen . during external data read/write operations, p0 functions as the data i/o bus. it is held in a high-impedance state for external reads from data memory, and driven with data during external writes to data memory. a page miss occurs when the msb of the subsequent address is different from the last address. the external memory machine cycle can be 2, 4, or 8 system clocks in length for a page miss. a page hit occurs when the msb of the subsequent address does not change from the last address. the external memory machine cycle can be 1, 2, or 4 system clocks in length for a page hit. during a page hit, p2 drives addr0?7 of the 16-bit address while the most significant address byte is held in the external address latches. psen , rd , and wr strobe accordingly for the appropriate operation on the p0 data bus. there is no ale assertion for page hits. during a page miss, p2 drives the addr [8:15] of the 16-bit address and holds it for the duration of the first half of the memory cycle to allow the external address latches to latch the new most significant address byte. ale is asserted to strobe the external address latches. during this operation, psen , rd , and wr are held in inactive states and p0 is in a high-impedance state. the second half of the memory cycle is executed as a page-hit cycle and the appropriate operation takes place. a page miss can occur at set intervals or during external operations that require a memory access into a page of memory that has not been accessed during the last external cycle. generally, the first external memory access causes a page miss. the new page address is stored internally, and is used to detect a page miss for the current external memory cycle.
ds89c420 ultra-high-speed microcontroller 29 of 47 note that there are a few exceptions for this mode of operation when pages1 and pages2 are set to 00b: psen is asserted for both page hit and page miss for a full clock cycle. the execution of external movx instruction causes a page miss. a page miss occurs when fetching the next external instruction following the execution of an external movx instruction. figure 11 shows the external memory cycle for this bus structure. the first case illustrates a back-to-back execution sequence for 1-cycle page mode (pages1 = pages0 = 0b). psen remains active during page-hit cycles, and page misses are forced during and after movx executions, independent of the most significant byte of the subsequent addresses. the second case illustrates a movx execution sequence for 2-cycle page mode (pages1 = 0 and pages0 = 1). psen is active for a full clock cycle in code fetches. note that changing the msb of the data address causes the page misses in this sequence. the third case illustrates a movx execution sequence for 4-cycle page mode (pages1 = 1 and pages0 = 0). there is no page miss in this execution cycle because the most significant byte of the data address is assumed to match the last program address. the second page mode (page mode 2) external bus structure multiplexes the most significant address byte with data on p2, and uses p0 for the least significant address byte. this bus structure is used to speed up external code fetches only. external data-memory access cycles are identical to the non-page mode except for the different signals on p0 and p2. figure 12 illustrates the memory cycle for external code fetches.
ds89c420 ultra-high-speed microcontroller 30 of 47 figure 11. page mode 1, external memory cycle (cd1:cd0 = 10) internal memory cycles xtal1 ale port 0 port 2 data data inst msb msb msb msb msb lsb lsb lsb lsb lsb lsb inst inst external memory cycles page miss page hit page miss data access data access pages=00 ale psen movx inst data page miss page miss data access page hit msbadd lsb add lsb add msbadd msbadd lsb add pages=01 port 0 port 2 msbadd lsb add lsb add inst data port 2 port 0 psen ale page miss data access rd / wr rd / wr pages=10 rd / wr movx movx lsb psen movx executed movx executed movx executed next instruction
ds89c420 ultra-high-speed microcontroller 31 of 47 figure 12. page mode 2, external code fetch cycle (cd1:cd0 = 10) internal memory cycles c2 c3 c4 c1 c2 c1 c2 xtal1 ale port 0 port 2 psen c1 ext code fetches page miss page hit page hit data data lsb add lsb add lsb add data msb add stretch external data memory cycle in page mode the ds89c420 allows software to adjust the speed of external data memory access by stretching the memory bus cycle in page mode operation just like non-page mode operation. the following tables summarize the stretch values and their effects on the external movx-memory bus cycle and the control signals? pulse width in terms of the number of oscillator clo cks. a stretch machine cycle always contains four system clocks, independent of the logic value of the page mode select bits. table 7. page mode 1, data memory cycle stretch values (pages1:pages0 = 00) rd/wr pulse width (in number of oscillator clocks) md2:md0 stretch cycles 4x/ 2x , cd1, cd0 = 100 4x/ 2x , cd1, cd0 = 000 4x/ 2x , cd1, cd0 = x10 4x/ 2x , cd1, cd0 = x11 000 0 0.25 0.5 1 1024 001 1 0.75 1.5 3 3072 010 2 1.75 3.5 7 7168 011 3 2.75 5.5 11 11,264 100 7 3.75 7.5 15 15,360 101 8 4.75 9.5 19 19,456 110 9 5.75 11.5 23 23,552 111 10 6.75 13.5 27 27,648 table 8. page mode 1, data memory cycle stretch values (pages1:pages0 = 01) rd / wr pulse width (in number of oscillator clocks) md2:md0 stretch cycles 4x/ 2x , cd1, cd0 = 100 4x/ 2x , cd1, cd0 = 000 4x/ 2x , cd1, cd0 = x10 4x/ 2x , cd1, cd0 = x11 000 0 0.25 0.5 1 1024 001 1 0.75 1.5 3 3072 010 2 1.75 3.5 7 7168 011 3 2.75 5.5 11 11,264 100 7 3.75 7.5 15 15,360 101 8 4.75 9.5 19 19,456 110 9 5.75 11.5 23 23,552 111 10 6.75 13.5 27 27,648
ds89c420 ultra-high-speed microcontroller 32 of 47 table 9. page mode 1, data memory cycle stretch values (pages1:pages0 = 10) rd / wr pulse width (in number of oscillator clocks) md2:md0 stretch cycles 4x/ 2x , cd1, cd0 = 100 4x/ 2x , cd1, cd0 = 000 4x/ 2x , cd1, cd0 = x10 4x/ 2x , cd1, cd0 = x11 000 0 0.5 1 2 2048 001 1 1 2 4 4096 010 2 2 4 8 8192 011 3 3 6 12 12,288 100 7 4 8 16 16,384 101 8 5 10 20 20,480 110 9 6 12 24 24,576 111 10 7 14 28 28,672 table 10. page mode 2, data memory cycle stretch values (pages1:pages0 = 11) rd / wr pulse width (in number of oscillator clocks) md2:md0 stretch cycles 4x/ 2x , cd1, cd0 = 100 4x/ 2x , cd1, cd0 = 000 4x/ 2x , cd1, cd0 = x10 4x/ 2x , cd1, cd0 = x11 000 0 0.5 1 2 2048 001 1 1 2 4 4096 010 2 2 4 8 8192 011 3 3 6 12 12,288 100 7 4 8 16 16,384 101 8 5 10 20 20,480 110 9 6 12 24 24,576 111 10 7 14 28 28,672 as shown in the previous tables, the stretch feature supports eight stretched external data-memory access cycles that can be categorized into three timing groups. when the stretch value is cleared to 000b, there is no stretch on external data-memory access and a movx instruction is completed in two basic memory cycles. when the stretch value is set to 1, 2, or 3, the external data memory access is extended by 1, 2, or 3 stretch memory cycles, respectively. note that the first stretch value does not result in adding four system clocks to the control signals. this is because the first stretch uses one system clock to create additional address setup and data bus float time, and one system clock to create additional address and data hold time. when using very slow ram and peripherals, a larger stretch value (4?7) can be selected. in this stretch category, two stretch cycles are used to create additional setup (the ale pulse width is also stretched by one stretch cycle for page miss) and one stretch cycle is used to create additional hold time. the following timing diagrams illustrate the external data-memory access at divide-by-1 system clock mode (cd1:cd0 = 10b).
ds89c420 ultra-high-speed microcontroller 33 of 47 figure 13. page mode 1, external data memory access (pages = 01, stretch = 1, cd = 10) ale psen port 0 port 2 ale port 0 port 2 rd / wr ale psen port 0 port 2 lsb addr lsb addr lsb addr lsb addr lsb addr lsb addr lsb addr lsb addr lsb addr lsb addr lsb addr lsb addr lsb addr lsb addr lsb addr lsb addr lsb addr lsb addr lsb addr lsb addr lsb addr inst inst inst inst inst inst inst inst inst inst inst inst inst inst inst data data movx movx movx msb addr msb addr msb addr data memory access (stretch =1) memory access (stretch =1) memory access (stretch =1) movx instruction movx instruction movx instruction movx inst fetch movx inst fetch xtal1 psen rd / wr rd / wr figure 13 illustrates the external data-memory stretch cycle timing relationship when pagee = 1 and pages1:pages0 = 01. the stretch cycle shown is for a stretch value of 1 and is coincident with a page miss. note that the first stretch value does not result in adding four system clocks to the rd/wr control signals. this is because the first stretch uses one system clock to create additional setup and one system clock to create additional hold time.
ds89c420 ultra-high-speed microcontroller 34 of 47 figure 14. page mode 1, external data memory access (pages = 01, stretch = 4, cd = 10) ale psen port 0 port 2 ale psen port 0 port 2 rd / wr xtal1 inst inst inst inst inst msb lsb lsb lsb lsb lsb lsb lsb inst data memory access (stretch = 4) movx instruction (page miss) 1st cycle 2nd cycle 3rd cycle 4th cycle 9th cycle movx instruction fetch lsb lsb lsb inst inst inst movx instruction (page hit) memory access (stretch = 4) movx instruction fetch 1st cycle 2nd cycle 3rd cycle 4th cycle 5th cycle 9th cycle lsb lsb lsb lsb inst inst inst inst rd / wr data lsb figure 14 shows the timing relationship for a slow peripheral interface (stretch value = 4). note that a page hit data- memory cycle is shorter than a page miss data-memory cycle. the ale pulse width is also stretched by a stretch cycle in the case of page miss. the stretched data-memory bus-cycle timing relationship for pages = 11 is identical to non-page mode operation since the basic data-memory cycle always contains four system clocks in this page mode operation. interrupts the ds89c420 provides 13 interrupt vector sources. all interrupts, with the exception of the power-fail, are controlled by a series combination of individual enable bits and a global enable (ea) in the interrupt enable register (ie.7). setting ea to logic 1 allows individual interrupts to be enabled. setting ea to a logic 0 disables all interrupts
ds89c420 ultra-high-speed microcontroller 35 of 47 regardless of the individual interrupt enable settings. the power-fail interrupt is controlled by its individual enable only. the interrupt enables and priorities are functionally identical to those of the 80c52, except that the ds89c420 supports five levels of interrupt priorities instead of the original two. interrupt priority there are five levels of interrupt priority: level 4 to 0. the highest interrupt priority is level 4, which is reserved for the power-fail interrupt. all other interrupts have individual priority bits in the interrupt priority registers to allow each interrupt to be assigned a priority level from 3 to 0. the power-fail interrupt always has the highest priority if it is enabled. all interrupts also have a natural hierarchy. in this manner, when a set of interrupts has been assigned the same priority, a second hierarchy determines which interrupt is allowed to take precedence. the natural hierarchy is determined by analyzing potential interrupts in a sequential manner with the order listed in table 11 . table 11. interrupt summary interrupt vector natural order flag enable priority control power-fail 33h 0 (highest) pfi (wdcon.4) epfi(wdcon.5) n/a external interrupt 0 03h 1 ie0 (tcon.1)** ex0 (ie.0) lpx0 (ip0.0) mpx0 (ip1.0) timer 0 overflow 0bh 2 tf0 (tcon.5)* et0 (ie.1) lpt0 (ip0.1) mpt0 (ip1.1) external interrupt 1 13h 3 ie1 (tcon.3)** ex1 (ie.2) lpx1 (ip0.2) mpx1 (ip1.2) timer 1 overflow 1bh 4 tf1 (tcon.7)* et1 (ie.3) lpt1 (ip0.3) mpt1 (ip1.3) serial port 0 23h 5 ri_0 (scon0.0) ti_0 (scon0.1) es0 (ie.4) lps0 (ip0.4) mps0 (ip1.4) timer 2 overflow 2bh 6 tf2 (t2con.7) exf2 (t2con.6) et2 (ie.5) lpt2 (ip0.5) mpt2 (ip1.5) serial port 1 3bh 7 ri_1 (scon1.0) ti_1 (scon1.1) es1 (ie.6) lps1 (ip0.6) mps1 (ip1.6) external interrupt 2 43h 8 ie2 (exif.4) ex2 (eie.0) lpx2 (eip0.0) mpx2 (eip1.0) external interrupt 3 4bh 9 ie3 (exif.5) ex3 (eie.1) lpx3 (eip0.1) mpx3 (eip1.1) external interrupt 4 53h 10 ie4 (exif.6) ex4 (eie.2) lpx4 (eip0.2) mpx4 (eip1.2) external interrupt 5 5bh 11 ie5 (exif.7) ex5 (eie.3) lpx5 (eip0.3) mpx5 (eip1.3) watchdog 63h 12 (lowest) wdif (wdcon.3) ewdi (eie.4) lpwdi (eip0.4) mpwdi (eip1.4) * cleared automatically by hardware when the service routine is vectored to. ** if the interrupt is edge triggered, cleared automatically by hardware when the service routine is vectored to. if the interrupt is level triggered, the flag follows the state of the pin. the processor indicates that an interrupt condition occurred by setting the respective flag bit. this bit is set regardless of whether the interrupt is enabled or disabled. unless marked in table 11, all these flags must be cleared by software. timer/counters three 16-bit timers are incorporated in the ds89c420. all three timers can be used as either counters of external events, where 1-to-0 transitions on a port pin are monitored and counted, or timers that count oscillator cycles. table 12 summarizes the timer functions. timers 0 and 1 both have three modes of operations. they can each be used as a 13-bit timer/counter, a 16-bit timer/counter, or an 8-bit timer/counter with auto-reload. timer 0 has a fourth operating mode as two 8-bit
ds89c420 ultra-high-speed microcontroller 36 of 47 timer/counters without auto-reload. each timer can also be used as a counter of external pulses on the corresponding t0/t1 pin for 1-to-0 transitions. the timer mode (tmod) register controls the operation mode. each timer consists of a 16-bit register in 2 bytes, which can be found in the sfr map as tl0, th0, tl1, and th1. the timer control (tcon) register enables timers 0 and 1. table 12. timer functions functions timer 0 timer 1 timer 2 timer/counter 13/16/8 * /2 x 8 bit 13/16/8 * bit 16 bit timer with capture no no yes external control-pulse counter yes yes no up/down auto-reload timer/counter no no yes baud rate generator no yes yes timer-output clock generator no no yes *8-bit timer/counter includes auto-reload feature; 2- x 8-bit mode does not. timer 2 is a true 16-bit timer/counter that, with a 16-bit capture (rcap2l and rcap2h) register, is able to provide some unique functions like up/down auto-reload timer/counter and timer-output clock generation. timer 2 (registers tl2 and th2) is enabled by the t2con register, and its mode of operation is selected by the t2mod register. each timer has a selectable time base ( table 14 ). following a reset, the timers default to divide-by-12 to maintain drop-in compatible with the 8051. if timer 2 is used as a baud rate generator or clock output, its time base is fixed at divide by 2, regardless of the setting of its timer mode bits. for details of operation, refer to ?programmable timers? in the ultra-high-speed flash microcontroller user?s guide . timed access the timed access function provides control verification to system functions. the timed access function prevents an errant cpu from making accidental changes to certain sfr bits that are considered vital to proper system operation. this is achieved by using software control when accessing the following sfr control bits: wdcon.0 rwt reset watchdog timer wdcon.1 ewt watchdog reset enable wdcon.3 wdif watchdog interrupt flag wdcon.6 por power-on reset flag exif.0 bgs bandgap select acon.5 pages0 page mode select bit 0 acon.6 pages1 page mode select bit 1 acon.7 pagee page mode enable romsize.0 rms0 program memory size select bit 0 romsize.1 rms1 program memory size select bit 1 romsize.2 rms2 program memory size select bit 2 romsize.3 prame program ram enable fcntl.0 fc0 flash command bit 0 fcntl.1 fc1 flash command bit 1 fcntl.2 fc2 flash command bit 2 fcntl.3 fc3 flash command bit 3
ds89c420 ultra-high-speed microcontroller 37 of 47 before these bits can be altered, the processor must execute the timed access sequence. this sequence consists of writing an aah to the timed access (ta, c7h) register, followed by writing a 55h to the same register within three machine cycles. this timed sequence of steps then allows any of the timed-access-protected sfr bits to be altered during the three machine cycles, following the writing of the 55h. writing to a timed access-protected bit outside of these three machine cycles has no effect on the bit. the timed-access process is address-, data-, and time-dependent. a processor running out of control and not executing system software cannot statistically perform this timed sequence of steps, and as such, will not accidentally alter the protected bits. it should be noted that this method should be used in the main body of the system software and never used in an interrupt routine in conjunction with the watchdog reset. interrupt routines using the timed-access watchdog-reset bit (rwt) can recover a lost system and allow the resetting of the watchdog, but the system returns to a lost condition once the reti is executed, unless the stack is modified. it is advisable that interrupts be disabled (ea = 0) when executing the timed-access sequence, since an interrupt during the sequence adds time, making the timed-access attempt fail. power management and clock-divide control the ds89c420 incorporates power management features that monitor the power-supply voltage levels and support low-power operation with three power-saving modes. such features include a bandgap voltage monitor, watchdog timer, selectable internal ring oscillator, and programmable system clock speed. the sfrs that provide control and application software access are the watchdog control (wdcon, d8h), extended interrupt enable (eie, e8h), extended interrupt flag (exif, 91h), and power control (pcon, 87h) registers. system clock-divide control the programmable clock-divide control bits (cd1 and cd0) provide the processor with the ability to adapt to different crystals and also to slow the system clocks providing lower power operation when required. an on-chip crystal multiplier allows the ds89c420 to operate at two or four times the crystal frequency by setting the 4x/ 2x bit and is enabled by setting the ctm bit to a logic 1. an additional circuit provides a clock source at divide-by-1024. when used with a 7.372mhz crystal, for example, the processor executes machine cycle in times ranging from 33.9ns (divide-by-0.25) to 138.9 s (multiply-by-1024), and maintains a highly accurate serial port baud rate while allowing the use of more cost-effective, lower-frequency crystals. although the clock-divide control bits can be written at any time, certain hardware features have been provided to enhance the use of these clock controls to guarantee proper serial port operation, and also to allow for a high-speed response to an external interrupt. the 01b setting of cd1 and cd0 is reserved, and has the same effect as the 10b setting, which forces the system clock into a divide by 1 mode. the ds89c420 defaults to divide-by-1 clock mode on all forms of reset. when programmed to the divide-by-1024 mode, and the switchback bit (pmr.5:swb) is also set, the system forces the clock-divide control bits to reset automatically to the divide-by-1 mode whenever the system has detected externally enabled interrupts. the oscillator divide ratios of 0.25, 0.5, and 1 are also used to provide standard baud-rate generation for the serial ports through a forced divide-by-12 input clock (txmh, txm = 00b, x = 1, 2, or 3) to the timers. when in divide-by-1024 mode, in order to allow a quick response to incoming data on a serial port, the system uses the switchback mode to automatically revert to divide-by-1 mode whenever a start bit is detected. this automatic switchback is only enabled during divide-by-1024 mode, and all other clock modes are unaffected by interrupts and serial port activity. see power management mode for more details. use of the divide-by-0.25 or 0.5 options through the clock-divide control bits requires that the crystal multiplier be enabled and the specific system-clock-multiply value be established by the 4x/ 2x bit in the pmr register. the multiplier is enabled through the ctm (pmr.4) bit but cannot be automatically selected until a startup delay has been established through the ckry bit in the status register. the 4x/ 2x bit can only be altered when the ctm bit is cleared to logic 0. this prevents the system from changing the multiplier until the system has moved back to the divide-by-1 mode and the multiplier has been disabled through the ctm bit. the ctm bit can only be altered when the cd1 and cd0 bits are set to divide-by-1 mode and the rgmd bit is cleared to 0. setting the ctm to logic 1 from a previous logic 0 automatically clears the ckry bit in the status register and starts the multiplier startup timeout in the multiplier startup counter. during the multiplier startup period the ckry bit remains cleared and the cd1 and cd0 clock controls cannot be set to 00b. the ctm bit is cleared to logic 0 on all resets. figure 15 gives a
ds89c420 ultra-high-speed microcontroller 38 of 47 simplified diagram of the generation of the system clocks. specifics of hardwar e restrictions associated with the use of the 4x/ 2x ctm, ckry, cd1, and cd0 bits are outlined in the sfr description. figure 15. system clock sources 4x/2 x ctm crystal oscillator divide 1024 ring oscillator clock multiplier cd0 cd1 selector ring enable mux system clock bandgap-monitored interrupt and reset generation the power monitor in the ds89c420 monitors the v cc pin in relation to the on-chip bandgap voltage reference. whenever v cc falls below v pfw , an interrupt is generated if the corresponding power-fail interrupt-enable bit epfi (wdcon.5) is set, causing the device to vector to address 33h. the power-fail interrupt-status bit pfi (wdcon.4) is set anytime v cc transitions below v pfw , and can only be cleared by software once set. similarly, as v cc falls below v rst , a reset is issued internally to halt program execution. following power-up, a power-on reset initiates a power-on reset timeout before starting program execution. when v cc is first applied to the ds89c420, the processor is held in reset until v cc > v rst and a delay of 65,536 oscillator cycles has elapsed, to ensure that power is within tolerance and the clock source has had time to stabilize. once the reset timeout period has elapsed, the reset condition is removed automatically and software execution begins at the reset vector location of 0000h. the power-on reset flag por (wdcon.6) is set to logic 1 to indicate a power-on reset has occurred, and can only be cleared by software. when the ds89c420 enters stop mode, the bandgap, reset comparator, and power-fail interrupt comparator are automatically disabled to conserve power, if the bgs (exif.0) bit is set to a logic 0. this is the lowest power mode. if bgs is set to logic 1, the bandgap reference, reset comparator, and the power-fail comparator are powered up, although in a reduced fashion, while in stop mode.
ds89c420 ultra-high-speed microcontroller 39 of 47 watchdog timer the watchdog timer functions as the source of both the watchdog interrupt and the watchdog reset. when the clock divider is set to 10b, the interrupt timeout has a default divide ratio of 2 17 of the crystal oscillator clock, with the watchdog reset set to timeout 512 system clock cycles later. this results in a 33mhz crystal oscillator producing an interrupt timeout every 3.9718ms, followed 15.5s later by a watchdog reset. the watchdog timer is reset to the default divide ratio following any reset. using the wd0 and wd1 bits in the clock control (ckcon.6 and 7) register, other divide ratios can be selected for longer watchdog interrupt periods. table 13 summarizes the watchdog bit settings and the timeout values. note: all watchdog-timer reset timeouts follow the programmed interrupt timeouts by 512 system clock cycles, which equates to varying numbers of oscillator cycles depending on the clock-divide (cd1:0) and crystal multiplier settings. table 13. watchdog timeout value (i n number of oscillator clocks) watchdog interrupt timeout watchdog reset timeout 4x/ 2x cd1:0 wd1:0 = 00 wd1:0 = 01 wd1:0 = 10 wd1:0 = 11 wd1:0 = 00 wd1:0 = 01 wd1:0 = 10 wd1:0 = 11 1 00 2 15 2 18 2 21 2 24 2 15 + 128 2 18 + 128 2 21 + 128 2 24 + 128 0 00 2 16 2 19 2 22 2 25 2 16 + 256 2 19 + 256 2 22 + 256 2 25 + 256 x 01 2 17 2 20 2 23 2 26 2 17 + 512 2 20 + 512 2 23 + 512 2 26 + 512 x 10 2 17 2 20 2 23 2 26 2 17 + 512 2 20 + 512 2 23 + 512 2 26 + 512 x 11 2 27 2 30 2 33 2 36 2 27 + 524,288 2 30 + 524,288 2 33 + 524,288 2 36 + 524,288 a watchdog control (wdcon) sfr is used for programming the functions. ewt (wdcon.1) is the enable for the watchdog-timer reset function and rwt (wdcon.0) is the bit used to restart the watchdog timer. setting the rwt bit restarts the timer for another full interval. if the watchdog timer reset function is masked by the ewt bit and no resets are issued to the timer through the rwt bit, the watchdog timer generates interrupt timeouts at a rate determined by the programmed divide ratio. wdif (wdcon.3) is the interrupt flag set at timer termination and wtrf (wdcon.2) is the reset flag set following a watchdog-reset timeout. the watchdog interrupt is enabled by the ewdi bit (eie.4) when it is set to 1. the watchdog timer reset and interrupt timeouts are measured by counting system clock cycles. an independent watchdog timer functions as the crystal startup counter to count 65,536 crystal clock cycles before allowing the crystal oscillator to function as the system clock. this warmup time is verified by the watchdog timer following each power-up as well as each time the crystal is restarted following a stop mode. the watchdog is also used to establish a startup time whenever the ctm in the pmr register is set to enable the crystal multiplier (4x / 2x ). one of the applications of the watchdog timer is for the watchdog to wake up the system from idle mode. the watchdog interrupt can be programmed to allow a system to wake up periodically to sample the external world. external reset if the rst input is taken to a logic 1, the device is forced into a reset state. an external reset is accomplished by holding the rst pin high for at least 3 clock cycles while the oscillator is running. once the reset state is invoked, it is maintained as long as rst is pulled to logic 1. when the rst is removed, the processor exits the reset state within 4 clock cycles and begins execution at address 0000h. if a rst is applied while the processor is in stop mode, the rst causes the oscillator to begin running and forces the program counter to 0000h. there is a reset delay of 65,536 clock cycles to allow the oscillator to stabilize. the rst pin is a bidirectional i/o. if a reset is caused by a power-fail reset, a watchdog timer reset, or an internal system reset, an output-reset pulse is also generated at the rst pin. this reset pulse is asserted as long as an internal reset is asserted and may not be able to drive the reset signal out if the rst pin is connected to an rc circuit. connecting the rst pin to a capacitor does not affect the internal reset condition.
ds89c420 ultra-high-speed microcontroller 40 of 47 oscillator-fail detect the ds89c420 incorporates an oscillator fail-detect circuit that, when enabled, causes a reset if the crystal oscillator frequency falls below 20khz and holds the chip in reset with the ring oscillator operating. setting the ofde (pcon.4) bit to logic 1 enables the circuit. the ofde bit is only cleared from logic 1 to logic 0 by a power- fail reset or by software. a reset caused by an oscillator failure also sets the ofdf (pcon.5) to logic 1. this flag is cleared by software or power-on reset. note that this circuit does not force a reset when the oscillator is stopped by the software-enabled stop mode. power management mode power management mode offers a software-controllable power-saving scheme by providing a reduced instruction cycle speed, which allows the ds89c420 to continue to operate while using an internally divided version of the clock source to save power. power management mode is invoked by software setting the clock-divide control bits cd1 and cd0 (pmr.7-6) bits to 11b, which sets an operating rate of 1024 oscillator cycles for 1 machine cycle. on all forms of reset, the clock-divide control bits default to 10b, which selects 1 oscillator cycle per machine cycle. since the clock speed choice affects all functional logic including timers, the ds89c420 implements several hardware switchback features that allow the clock speed to automatically return to the divide-by-1 mode from a reduced cycle rate. setting the swb (pmr.5) bit to a 1 in software enables this switchback function. when cd1 and cd0 are programmed to the divide-by-1024 mode and the swb bit is also enabled, the system forces the clock-divide control bits to automatically reset to the divide-by-1 mode whenever the system detects an externally enabled (and allowed through nesting priorities) interrupt. the switchback occurs whenever one of the two conditions occur. the first switchback condition is initiated by the detection of a low on either int0 , int1 , int3 or int5 , or a high on int2 or int4 when the respective pin has been programmed and allowed (through nesting priorities) to issue an interrupt. the second switchback condition occurs when either serial port is enabled to receive data and is found to have an active-low transition on the respective receive input pin. serial port transmit activity also forces a switchback if the swb is set. note that the serial port activity, as related to the switchback, is independent of the serial port interrupt relationship. any attempt to change the clock divider to the divide-by-1024 mode while the serial port is either transmitting or receiving has no effect, leaving the clock control in the divide-by- 1 mode. note also that the switchback interrupt relationship requires that the respective external interrupt source is allowed to actually generate an interrupt as defined by the priority of the interrupt and the state of the nested interrupts, before the switchback can actually occur. an interrupt by the serial port is not required, nor is the setting of serial port enable. disabling external interrupts and serial port receive/transmission mode disable the automatic switchback mode. clearing the swb bit also disables the switchback, and all interrupt and serial port controls of the clock divider are disabled. all other clock modes ignore the switchback relationship and are unaffected by interrupts and serial port activity. the basic divide-by-12 mode for the timers (txmh, txm = 00b), as well as the divide-by-32 and 64 for mode 2 on the serial ports, are maintained when running the processor with the oscillator divide ratio of 0.25, 0.5, and 1. serial ports and timers track the oscillator cycles per machine cycle when the higher divide ratio of 1024 is selected, and require the switchback function to automatically return to the divide-by-1 mode for proper operation when a qualified event occurs. table 14 summarizes the effect of clock mode on timer operation. it is possible to enable a receive function on a serial port when incoming data is not present and then change to the higher divide ratio. an inactive serial port receive/transmit mode requires the receive input pin to remain high and all outgoing transmissions to be completed. during this inactive receive mode it is possible to change the clock- divide control bits from a divide-by-1 to a 1024 divide ratio. in the case when the serial port is being used to receive or transmit data it is very important to validate an attempted change in the clock-divide control bits (read cd1 and cd0 to verify write was allowed) before proceeding with low-power program functions.
ds89c420 ultra-high-speed microcontroller 41 of 47 table 14. effect of clock mode on timer op eration (in number of oscillator clocks) osc. cycles per timers (0, 1, 2) clock osc. cycles per timer 2 clock osc. cycles per serial port clock mode 0 osc. cycles per serial port clock mode 2 txmh, txm = 4x/2x, cd1, cd0 osc. cycles per machine cycle 00 01 1x baud rate generator t2mh, t2m = xx sm2 = 0 sm2 = 1 smod = 0 smod = 1 100 0.25 12 1 0.25 2 3 1 64 32 000 0.5 12 2 0.5 2 6 2 64 32 x01 1 (reserved) ? ? ? ? x10 1 (default) 12 4 1 2 12 4 64 32 x11 1,024 12,288 4,096 1,024 2,048 12,288 4,096 65,536 32,768 x = don?t care ring oscillator a ring oscillator, which typically runs at 10mhz, allows the processor to recover instantly from the stop mode. when the system is in stop mode the crystal is disabled. when stop mode is removed, the crystal requires a period of time to start up and stabilize. to allow the system to begin immediate execution of software following the removal of the stop mode, the ring oscillator is used to supply a system clock until the crystal startup time is satisfied. once this time has passed, the ring oscillator is switched off and the system clock is switched over to the crystal oscillator. this function is programmable and is enabled by setting the rgsl bit (exif.1) to logic 1. when it is logic 0, the processor delays software execution until after the 65,536 crystal clock periods. to allow the processor to know whether it is being clocked by the ring or the crystal oscillator, an additional bit, termed the rgmd bit, indicates which clock source is being used. when the processor is running from the ring, the clock- divide control bits (cd1 and cd0 in the pmr register) are locked into the divide-by-1 mode (cd1:cd0 = 10b). the clock-divide control bits cannot be changed from this state until after the system clock transitions to the crystal oscillator (rgmd = 0). note: the watchdog is permanently connected to the crystal oscillator and continues to run at the external clock rate. the ring oscillator does not drive it. idle mode idle mode suspends the processor by holding the program counter in a static state. no instructions are fetched and no processing occurs. setting the idle bit (pcon.0) to logic 1 invokes idle mode. the instruction that executes this step is the last instruction prior to freezing the program counter. once in idle mode, all resources are preserved but all peripheral clocks remain active, and the timers, watchdog, serial ports, and power monitor functions continue to operate, so that the processor can exit the idle mode using any interrupt sources that are enabled. the oscillator-detect circuit also continues to function when enabled. the idle bit is cleared automatically once idle mode is exited. on returning from the interrupt vector using the reti instruction, the next address is the one that immediately follows the instruction that invoked the idle mode. any processor resets also remove the idle mode. stop mode the stop mode disables all circuits within the processor. all on-chip clocks, timers, and serial port communication are stopped, and no processing is possible. stop mode is invoked by setting the stop bit (pcon.1) to logic 1. the processor enters the stop mode on the instruction that sets the bit. the processor can exit stop mode by using any of the six external interrupts that are enabled.
ds89c420 ultra-high-speed microcontroller 42 of 47 an external reset by the rst pin unconditionally exits the processor from stop mode. if the bgs bit is set to logic 1, the bandgap provides a reset while in stop mode if v cc should drop below the v rst level. if bgs is 0, no reset is generated if v cc drops below v rst . when the stop mode is removed, the processor waits for 65,536 clock cycles for the internal flash memory to warm up before starting normal execution. also, the processor waits for the crystal warmup period if not using the ring oscillator. serial i/o the ds89c420 provides a serial port (uart) that is identical to the 80c52. in addition, it includes a second hardware serial port that is a full duplicate of the standard one. this port optionally uses pins p1.2 (rxd1) and p1.3 (txd1) and has duplicate control functions included in new sfr locations. both ports can operate simultaneously but can be at different baud rates or even in different modes. the second serial port has similar control registers (scon1 at c0h, sbuf1 at c1h) as the original. the new serial port can only use timer 1 for timer-generated baud rates. control for serial port 0 is provided by the scon0 register while its i/o buffer is sbuf0. registers scon1 and sbuf1 provide the same functions for the second serial port. a full description of the use and operation of both serial ports is in the ultra-high-speed flash microcontroller user?s guide. instruction set the ds89c420 instructions are 100% binary compatible with the industry standard 8051, and are only different in the number of machine cycles used for the instructions. some special conditions and features should be considered when analyzing the ds89c420 instruction set. full details are given in the ultra-high-speed flash microcontroller user?s guide.
ds89c420 ultra-high-speed microcontroller 43 of 47 package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/dallaspackinfo .) pkg 40-pin dim min max a ? 0.200 a1 0.015 ? a2 0.140 0.160 b 0.014 0.022 c 0.008 0.012 d 1.980 2.085 e 0.600 0.625 e1 0.530 0.555 e 0.090 0.110 l 0.115 0.145 eb 0.600 0.700 56 ? g5000 ? 000 dimensions are in inches (in).
ds89c420 ultra-high-speed microcontroller 44 of 47 note 1: pin 1 identifier to be located in zone indicated. note 2: controlling dimensions are in inches (in).
ds89c420 ultra-high-speed microcontroller 45 of 47
ds89c420 ultra-high-speed microcontroller 46 of 47 pin configurations 6 1 40 18 28 7 39 17 29 dallas semiconductor ds89c420 top view plcc 33 23 1 11 34 22 44 12 dallas semiconductor ds89c420 top view tqfp p1.0/t2 p1.1/t2ex p1.2/rxd1 p1.3/txd1 p1.4/int2 p1.5/int3 p1.6/int4 p1.7/int5 rst p3.0/rxd0 p3.1/txd0 p3.2/int0 p3.3/int1 p3.4/t0 p3.5/t1 p3.6/wr p3.7/rd xtal2 xtal1 v ss v cc p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 ea/vpp a le/prog psen p2.7 p2.6 p2.5 p2.4 p2.3 p2.2 p2.1 p2.0 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 ds89c420 dip top view
ds89c420 ultra-high-speed microcontroller 47 of 47 maxim/dallas semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a ma xim/dallas semiconductor product. no circuit patent licenses are implied. maxim/dallas semiconductor reserves the right to change the circuitry and specification s without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2005 maxim integrated products printed usa the maxim logo is a registered trademark of maxim integrated products, inc. the dallas logo is a registered trademark of dallas semiconductor. revision history revision description 092200 initial release 122601 added errata (see www.maxim-ic.com/errata for details.) 042702 official product introduction release 051302 inserted ac characteristics table 103102 removed (min operating voltage) from dc electrical characteristics ; inserted diagram of rom loader interface circuit 032003 added 25mhz variant information 102203 modified figure 7 to support programmer-only operation. 081805 clarified availability of progamming software. corrected min/max external clock speed table in note 1. removed detailed parallel programming instructions and repalced with a note to contact factory for more information.

▲Up To Search▲

Price & Availability of DS89C420-QNG

	To Download DS89C420-QNG Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .